This invention relates to a semiconductor integrated circuit containing plural functional blocks.
As the density of components on semiconductor integrated circuits and the speed of operation increase, the size of semiconductor chips and power consumption increase. Accordingly, it is increasingly becoming important that functional blocks in a semiconductor integrated circuit are stably fed clock pulses and electric current.
In a conventional semiconductor integrated circuit having a multi-level metal interconnect-wiring configuration, there are no interconnect-wiring limitations in a metal interconnect-wiring layer, and it is so intended that the area occupied by metal interconnect-wirings connected to functional blocks is reduced to a minimum.
A first conventional semiconductor integrated circuit is explained. A clock signal line and a power supply line of such a circuit are detailed.
FIG. 10 is an illustration showing a clock signal line and a power supply line in a conventional semiconductor integrated circuit. A clock input pad, indicated by reference numeral 80, is provided on the periphery of a semiconductor chip. A clock driver, indicated by reference numeral 81, is provided, which locates next to the clock input pad 80. Functional blocks, indicated by reference numerals 82, 83, 84, and 85, are provided in the semiconductor chip, each functional block containing a clock pulse generator. A V.sub.DD power supply line is indicated by reference numeral 86. A V.sub.SS power supply line (ground) is indicated by reference numeral 87. A clock signal line, indicated by reference numeral 88, is a transmission line through which clock signals sent out from the clock driver 81 are transmitted to the clock pulse generators in the functional blocks 82, 83, 84, and 85.
In the above-described semiconductor integrated circuit, the clock signal line 88 has priority of interconnect-wiring over other signal lines, which allows the clock signal line 88 to run to a clock pulse generator by shortest.
However, in the first conventional semiconductor integrated circuit, the area occupied by a power supply line or a clock signal line becomes greater as the density of components on a semiconductor chip becomes higher. Additionally, a clock signal line lengthens as the size of a semiconductor chip increases. This causes a greater difference in the interconnect-wiring length of a clock signal line, between functional blocks. The clock skew between functional blocks becomes serious, accordingly.
In accordance with this prior art technique, an uppermost-level metal interconnect-wiring layer is provided with signal lines of the functional blocks 82, 83, 84, and 85, in addition to the clock signal line 88, the V.sub.DD power supply line 86, and the V.sub.SS power supply line 87. For the case of a semiconductor integrated circuit having a multi-level interconnect-wiring layer, the metal interconnect-wiring of an upper-level layer is likely to be damaged due to the difference in film thickness of the metal interconnect-wiring of a lower-level layer. This presents a drawback that the fabrication of semiconductor integrated circuits with a multi-level metal interconnect-wiring layer is difficult.
Japanese Patent Application, published under No. 64-57736, discloses a second conventional semiconductor integrated circuit.
This semiconductor integrated circuit intends to reduce the value of resistance of a clock signal line of the foregoing first conventional semiconductor integrated circuit. In this semiconductor integrated circuit, an uppermost-level metal interconnect-wiring layer is exclusively used for the interconnect-wiring of a clock signal line. Such an upper-most-level layer is a non-etched, flat layer for the supply of clock signals.
Since, in the second conventional semiconductor integrated circuit, a non-etched flat layer constitutes a clock signal line, this reduces the value of resistance thereof. However, the capacitance of interconnect-wiring is over 500 times that of the prior art interconnect-wiring. More time and power are consumed to drive a clock signal. This prior art technique seems characterized in that it requires no etching steps in processing. However, an external input pad must be provided on an uppermost-level layer, which necessitates etching for distinguishing a clock signal line from an external input pad. Further, the power supply lines are not different from those in the prior art techniques so that the area of a semiconductor chip inevitably increases. Although the clock skew between functional blocks is canceled using the second conventional semiconductor integrated circuit, there are several disadvantages which prevent such a semiconductor integrated circuit from being put into practical applications.
Japanese Patent Application, published under No. 1-289155, discloses a third conventional semiconductor integrated circuit.
This third semiconductor integrated circuit employs a clock signal feed method. A single clock pulse generator is provided at the center of a semiconductor chip. A clock driver sends out clock signals to the single-provided clock pulse generator. Upon receiving a clock signal, the clock pulse generator directly drives each functional block. This semiconductor integrated circuit intends to reduce the clock skew between functional blocks by making the interconnect-wiring lengths from one clock pulse generator to each functional block almost equal.
The third conventional semiconductor integrated circuit, however, has some disadvantages. Although the arrangement of providing a single clock pulse generator at the center of a semiconductor chip produces the foregoing advantage that the interconnect-wiring lengths from on single clock pulse generator to each functional block become almost equal, it presents several problems that a greater voltage drop occurs since the distance between a clock pulse generator and a power pad lengthens. Furthermore, a logical circuit, which shares the same power supply line with the clock pulse generator, suffers noises, since only one clock pulse generator is provided thereby consuming much power and causing a voltage drop.
In this conventional semiconductor integrated circuit, the distance between a clock pulse generator and a functional block still stays lengthy so that the difference in distance between a clock pulse generator and a functional block is still existent. In consequence, the clock skew will not be suppressed effectively.